The present invention relates to a semiconductor device and a method of manufacturing the same, and for example, to a technology that can be applied to a semiconductor device having a structure in which a first wiring and a second wiring are coupled by using a coupling member.
The semiconductor device has a multilayer wiring structure in order to route wirings. In addition, a first wiring located in a relatively low layer and a second wiring located in a layer that is higher than the low layer are coupled to each other via a coupling member such as a via or a contact.
For example, Japanese Patent Laid-Open No. 2006-13078 (Patent Literature 1) describes that the via is extended obliquely.
Furthermore, Japanese Patent Laid-Open No. 2009-141334 (Patent Literature 2) describes that the inclination of a part of the side surface of the via is made more gradual than that of other portions of the side surface of the via.